1. Field of the Invention
The present invention relates to a delta-sigma modulator and an A/D converter provided with a delta-sigma modulator, and, for example, relates to a delta-sigma modulator and an A/D converter provided with a delta-sigma modulator used in a recording apparatus for two channel analog signals (Lch/Rch).
2. Description of Related Art
In the related art, an equipment provided with a delta-sigma modulator which performs differentiation and integration processing on analog input and transmits digital output with a small number of bits such as one bit is well known as an A/D converter. Normally, the digital output of a small number of bits from the delta-sigma modulator is converted to digital output of a large number of bits using a decimation circuit such as a digital filter.
FIG. 1 illustrates the principle of operation of an A/D converter provided with a delta-sigma modulator.
As shown in FIG. 1, from an analog input signal applied to input terminal 1, a reference analog voltage which is output of one bit of D/A converter 14 is subtracted by adder 11, and this differential signal is integrated by integrator 12. This integrated signal is then quantized to a digital signal by quantizer 13. This quantized signal is inputted to D/A converter 14, and inputted to adder 11 as a reference analog voltage. A circuit configured with adder 11, integrator 12, quantizer 13 and D/A converter 14 is referred to as delta-sigma modulator 10, and the output of quantizer 13 is transmitted to delta-sigma modulator output terminal 2. The output of delta-sigma modulator 10 is decimated by digital filter 15, and an N-bit digital signal is transmitted to A/D converter output terminal 3.
Next, the detailed operation of an A/D converter provided with a delta-sigma modulator will be described.
FIG. 2 is a circuit diagram showing a specific configuration of the A/D converter provided with the delta-sigma modulator. Components that are the same as those in FIG. 1 will be assigned the same reference numerals.
In FIG. 2, 1 is an input terminal, 2 is a delta-sigma modulator output terminal, 3 is an A/D converter output terminal, 21 to 24 and 31 to 34 are analog switches, 25, 35 and 45 are capacitor elements, 40 is an operational amplifier, and 41 is a quantizer. The output of quantizer 41 is decimated by digital filter 15 and inputted to switch control circuit 50. Switch control circuit 50 controls analog switches 21 to 24 and 31 to 34, and this path configures D/A converter 51 for charging reference voltage VR. Operational amplifier 40 and capacitor element 45 configure an integrator, and charge of the charged capacitor is integrated by capacitor element 45.
The above-described analog switches 21 to 24 and 31 to 34, capacitor elements 25, 35 and 45, operational amplifier 40, quantizer 41 and switch control circuit 50 configure delta-sigma modulator 20.
When this delta-sigma modulator 20 reaches a state of equilibrium, the input signal is charged to capacitor element 25, while a sampling period of charging reference voltage VR according to the output of quantizer 41 to capacitor element 35 and an integration period of charging charge of capacitor elements 25 and 35 to capacitor element 45 are repeated.
During the sampling period, switches 21 and 23 are turned on, switches 22 and 24 are turned off, and input voltage Vin is charged to capacitor element 25, while switches 31 to 34 are controlled via switch control circuit 50 so that the output result of quantizer 41 is D/A converted to capacitor element 35.
During the integration period, switches 21 and 23 are turned off, switches 22 and 24 are turned on, and switches 31 to 34 are controlled via switch control circuit 50 so that capacitor element 45 is charged with addition of the charge of capacitor element 25 and capacitor element 35.
By operating the above-described delta sigma modulator 20 at an extremely high frequency compared to the input signal frequency, quantization noise generated by quantizer 41 is focused on high-frequency band compared to the input signal frequency band. At this time, the quantization noise is distributed in the higher-frequency band when the ratio between the operating frequency (sampling frequency) of the circuit and the input signal frequency—the oversampling ratio—is higher, so that a high S/N can be obtained as an A/D converter.
However, with the above-described technique, only one channel of input signal can be processed with one delta-sigma modulator, and it is therefore necessary to provide delta-sigma modulators in parallel according to the number of channels in order to process input signals of a plurality of channels. When the AID converter provided with a delta-sigma modulator is subjected to LSI (Large Scale Integration), the dimension of the delta-sigma modulator on the semiconductor chip is large compared to other circuit elements. As a result, when the number of delta-sigma modulators increases according to increase in the number of channels, there is a problem that the chip size increases substantially in proportion to the number of channels, and the equipment becomes large.
As the related art which resolves the above-described problem, patent document 1 (Japanese Patent Application Laid-Open No. HEI. 7-249989) discloses an A/D converter provided with the delta-sigma modulator described above. The delta-sigma modulator of patent document 1 is a delta-sigma modulator having: a switching section that sequentially and selectively switches analog input of a plurality of channels and transmits the result as a time-divided input; a plurality of capacitors corresponding to the plurality of channels, that are sigma-delta modulators that perform differentiation and integration processing on the time-divided input from the switching section and transmit the time-divided digital output; and a section that carries out integration by switching to a capacitor for integration corresponding to each channel, and transmits the time-divided digital output.
FIG. 3 is a circuit diagram showing a specific configuration of the A/D converter provided with the delta-sigma modulator disclosed in patent document 1. Components that are the same as those in FIG. 2 will be assigned the same reference numerals.
In FIG. 3, 51 and 52 are input terminals, 53 is a delta-sigma modulator output terminal, 54 and 55 are A/D converter output terminals, 21 to 24, 31 to 34, 61 and 62 are analog switches, 25, 35, 45 and 55 are capacitor elements, 40 is an operational amplifier, 41 is a quantizer, 63 is a switcher, 64 is a divider, and 65 and 66 are digital filters.
Switcher 63 alternately digital-division inputs input signals A and B, and the output of quantizer 41 is transmitted to delta-sigma modulator output terminal 53 according to this. Divider 64 alternately transmits the output of quantizer 41 to digital filters 65 and 66 according to the input signal. The output of quantizer 41 controls analog switches 21 to 24 and 31 to 34, 61 and 62 via switch control circuit 60, and this path configures D/A converter 61 that charges reference voltage VR. Operational amplifier 40 and capacitor element 45, or capacitor element 55 configure an integrator, and the charge of the charged capacitor is integrated by capacitor element 45 and capacitor element 55.
The above-described analog switches 21 to 24 and 31 to 34, 61 and 62, capacitor elements 25, 35, 45 and 55, operational amplifier 40, quantizer 41, and switch control circuit 60 configure delta-sigma modulator 70.
When this delta-sigma modulator 70 reaches a state of equilibrium, input signal A is charged to capacitor element 25, while a sampling period of sampling input signal A which is charged to capacitor element 35 with reference voltage VR according to the output of quantizer 41 and an integration period of integrating input signal A which is charged to capacitor element 45 with charge of capacitor elements 25 and 35 are sequentially repeated. At the same time, input signal B is charged to capacitor element 25, while a sampling period of sampling input signal B which is charged to capacitor element 35 with reference voltage VR according to the output of quantizer 41 and an integration period of integrating input signal B which is charged to capacitor element 55 with charge of capacitor elements 25 and 35 are sequentially repeated.
During the sampling period of input signal A, input signal A is selected by switcher 63, switches 21 and 23 are turned on, switches 22 and 24 are turned off, and, capacitor element 25 is charged with Vin a of input voltage A, while switches 31 to 34 are controlled via switch control circuit 60 so that the output result of quantizer 41 is D/A converted to capacitor element 35. Further, the output of quantizer 41 is transmitted to digital filter 65 via divider 64.
During the integration period of input signal A, switches 21, 23 and 62 are turned off, switches 22, 24 and 61 are turned on, and switches 31 to 34 are controlled via switch control circuit 60 so that capacitor element 45 is charged with addition of the charge of capacitor element 25 and capacitor element 35.
During the sampling period of input signal B, input signal B is selected by switcher 63, switches 21 and 23 are turned on, switches 22 and 24 are turned off, and capacitor element 25 is charged with Vin b of input voltage B, while switches 31 to 34 are controlled via switch control circuit 60 so that the output result of quantizer 41 is D/A converted to capacitor element 35. Further, the output of quantizer 41 is transmitted to digital filter 66 via divider 64.
During the integration period of input signal B, switches 21, 23 and 61 are turned off, switches 22, 24 and 62 are turned on, and switches 31 to 34 are controlled via switch control circuit 60 so that capacitor element 55 is charged with addition of the charge of capacitor element 25 and capacitor element 35.
However, with such an AID converter provided with the delta-sigma modulator of the related art, the analog input of two channels is supplied to the delta-sigma modulator by a time-division input switching section. Therefore, the oversampling ratio is ½ times compared to a delta-sigma modulator which processes analog input of one channel using one delta-sigma modulator, and S/N (resolution) deteriorates.
The resolution of the delta-sigma modulator depends on the oversampling ratio. For example, with a second order delta-sigma modulator, by doubling the oversampling ratio, resolution is improved by 2.5 bits, and, with a third order modulator, by doubling the oversampling ratio, resolution is improved by 3.5 bits. As a result, it is preferable to operate at an oversampling ratio as high as possible. However, when the oversampling ratio is made high, the operating speed of the circuit also increases in proportion to the oversampling ratio, and therefore the current consumption also increases.
That is, in the related art, when the oversampling ratio is made one time compared to the delta-sigma modulator which processes analog input of one channel using one delta-sigma modulator, the operating speed of the circuit is doubled, and there is a problem that current consumption increases.